In PG5 SP1.2.130 the analogue module PCD3.W745 isn't implemented. To be able to configure the PCD3.W745 on a PCD3.RIO the latest *.gsd file is required.
The PCD must be equipped with a PCD7.F8xx module and RAM is to be mounted on the memory socket, with the "memory use" set to RAM (the binding does not work with a Flash).
It's possible to open or close a connection of S-Web-Connect (WebConnect 2.x) to a PCD with the use of a URL address:
There is a possibility to update the firmware of a PCD2.F2xxx or PCD3.F2xx, in this FAQ it is explained how to proceed.
The first generation of PCDs with integrated S-Web server did not support http-direct (e.g. the PCD1.M125, PCD1.M135, PCD2.M150, PCD2.M170, PCD2.M480) . Therefore the access of the S-Web Server must be realized using the free software "S-WebConnect" which is to be installed on a PC (accessing the PCD using e.g. Ether-S-Bus). Alternatively, an MB Panel can also access the S-Web Server (e.g. using Ether-S-Bus). However, it is important to know that only one S-Bus client can access the S-Web Server over Ether-S-Bus at the same time!
Up to 13 free configurable rows for configuration of the I/O data exchange area can be inserted in "HW Config".
The system catalog mentionned 6 digital inputs (24 Volt, 4 x interrupts) and 2 digital outputs (2 x PWM, 24V 100 mA). But in reality only 4 digital inputs (not 6) are available at the moment and 2 digital outputs as mentionned in HW manual!
Since BACnet objects vary heavily in the amount of properties and features it is not possible to define a number of supported BACnet objects per CPU. However, this FAQ contains a rule of thumb for the amount of BACnet objects that can be defined on a PCD3 or a PCD2.M5xx0.
A 2,2 voltage of the battery is sufficient to keep the content of the SRAM memory of the PCD even if the PCD is not powered on with the 24VDC. At power-up, the PCD checks if the battery or supeCAP voltage is less than 2.2. volt, and tests some patterns and signatures in the SRAM. If one of those test gives an error the content of the SRAM is deleted, the PCD clock is reinitialized. If a Program Backup is available, a restore is done.
The FBox "Initialisation 2.0" from the DDC Suite FBox library has a "WD" input. When activated, this will close the onboard watchdog relay of the PCD (and open it if an error on the PCD occurs or if the user program takes more than 250 ms to be executed).
